This invention relates to programmable logic device integrated circuits, and more particularly, to testing programmable logic devices.
Programmable logic devices are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design (CAD) tools to design a custom logic circuit. These tools help the designer to implement the custom logic circuit using the resources available on a given programmable logic device. When the design process is complete, the CAD tools generate configuration data files. The configuration data is loaded into programmable logic devices to configure them to perform the desired custom logic function.
Programmable logic devices generally contain blocks or regions of random-access memory (RAM). These memory blocks, which are sometimes referred to as embedded array blocks (EABs) are used to handle the storage needs of the circuitry on the device. During normal operation of a programmable logic device, the hardwired and programmable circuitry of the device performs read and write operations on the memory of the blocks. Memory blocks on a programmable logic device typically range in size from a few kilobits to about a megabit or more.
Programmable logic devices are tested during manufacturing. Some programmable logic devices contain redundant circuitry. If testing reveals that a device contains a defect, the device can be repaired by switching the redundant circuitry into use. When testing identifies a defect that cannot be repaired, the device may be discarded. After testing and any necessary repairs have been completed, the device can be programmed for normal operation in a system.
The ability to perform detailed tests on circuitry such as programmable logic device memory block circuitry can be particularly critical during the early phases of product development. These detailed tests can reveal design or process problems. By addressing these problems early during the development of a programmable logic device, the design of the device can be improved to eliminate any process sensitivity or the manufacturing process can be tuned to enhance manufacturing yields.
Conventional memory block testing techniques are generally unable to produce detailed memory block test results. Tests are often performed below normal clock speeds. Tests at normal clocks speeds, which are sometimes referred to as at-speed tests, reveal faults that would otherwise not appear and are therefore critical for thorough testing. Conventional tests are also often unable to produce bit-mapped results. Without bit-mapped data from at-speed memory tests, it can be difficult or impossible to fully eliminate bugs and enhance manufacturing yields.
It would therefore be desirable to be able to produce bit-mapped tests results for at-speed programmable logic device memory tests.